Embodiments of the inventive concept relate generally to semiconductor memory devices. More particularly, embodiments of the inventive concept relate to flash memory devices comprising multi-level memory cells, flash memory systems incorporating the flash memory devices, and methods of programming the flash memory devices.
Semiconductor memory devices can be roughly divided into two categories based on whether or not they retain stored data when disconnected from power. These categories include nonvolatile memory devices, which retain stored data when disconnected from power, and volatile memory devices, which lose stored data when disconnected from power. Examples of nonvolatile memory devices include mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory. Examples of volatile memory include dynamic random access memory (DRAM) and static random access memory (SRAM).
In recent years, increasing demand for high capacity data storage has led to the development of various types of nonvolatile memory that can store multiple bits of data per memory cell. Such memory cells are commonly referred to as multi-level memory cells. As examples, some flash memory devices have been developed with multi-level cells that store two bit data using four threshold voltage distributions corresponding to logic states “11”, “01”, “00”, and “10”, and some flash memory devices have been developed with multi-level cells that store three bit data using eight threshold voltage distributions. By contrast, single-level memory cells store one bit data using two threshold voltage distributions corresponding to logic states “1” and “0”.
Memory cells that store more bits of data tend to have smaller distances between adjacent threshold voltage distributions compared with memory cells that store fewer bits of data. Consequently, a greater level of precision is generally required to distinguish between threshold voltage distributions of multi-bit memory cells compared with single-level memory cells. Moreover, in memory cells with smaller distances between adjacent threshold voltage distributions, electrical interference, such as coupling with adjacent memory cells, can cause adjacent threshold voltage distributions to overlap, which can cause read errors or other malfunctions.